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A Parallel-Layered Belief-Propagation Decoder for Non-layered LDPC Codes., , and . J. Commun., 5 (5): 400-408 (2010)A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (1): 106-110 (2019)An Energy-Efficient Level Shifter for Ultra Low-Voltage Digital LSIs., , , , and . IEEE Trans. Circuits Syst., 67-II (12): 3357-3361 (2020)A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes., , , , , and . IEICE Electron. Express, 14 (15): 20170660 (2017)Erratum: Snake: An asynchronous pipeline for ultra-low-power applications IEICE Electronics Express Vol. 16 (2019) No. 12 pp. 20190293., , , , and . IEICE Electron. Express, 17 (17): 20208001 (2020)An ultra-low leakage energy efficient level shifter with wide conversion range., , , , , and . IEICE Electron. Express, 16 (19): 20190507 (2019)Erratum: A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170660., , , , , and . IEICE Electron. Express, 14 (22): 20178005 (2017)Snake: An asynchronous pipeline for ultra-low-power applications., , , , and . IEICE Electron. Express, 16 (12): 20190293 (2019)A low power and glitch-free circular rotation phase modulator for outphasing transmitter., , , and . IEICE Electron. Express, 15 (14): 20180406 (2018)A Low Power, High Performance Analog Front-End Circuit for 1 V Digital Hearing Aid SoC., , , and . CSSP, 34 (5): 1391-1404 (2015)