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Assessment of on-chip wire-length distribution models., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (10): 1108-1112 (2004)Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models., , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (12): 1330-1347 (2004)Multi-tier dynamic sampling weak RF signal estimation theory., and . EURASIP J. Adv. Signal Process., 2024 (1): 7 (December 2024)Quantization error for weak RF simultaneous signal estimation., , and . EURASIP J. Adv. Signal Process., 2023 (1): 89 (December 2023)Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection requirements., , and . IBM J. Res. Dev., 49 (4-5): 777-803 (2005)Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry., , and . SLIP, page 43-50. ACM, (2005)Impact of interconnect length changes on effective materials properties (dielectric constant)., , and . SLIP, page 73-80. ACM, (2007)Erratum., and . IEEE Trans. Aerosp. Electron. Syst., 51 (3): 2519 (2015)Theoretical phase calculation approach for N simultaneous signals., , and . IEEE Trans. Aerosp. Electron. Syst., 51 (2): 878-883 (2015)Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution., , , , and . ACM Great Lakes Symposium on VLSI, page 38-43. ACM, (2005)