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Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins.

D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu. CoRR, (2018)

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Praveen Seshadri

Sangeetha Seshadri

Varadarajan Seshadri

Nagarajavel Vivekananthan

Vivek Venkataramani

Other publications of authors with the same name

Adaptive-Latency DRAM (AL-DRAM).D. Lee, Y. Kim, G. Pekhimenko, S. Khan, V. Seshadri, K. Chang, and O. Mutlu. CoRR, (2016)Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency.H. Hassan, G. Pekhimenko, N. Vijaykumar, V. Seshadri, D. Lee, O. Ergin, and O. Mutlu. CoRR, (2018)RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization.V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. Gibbons, M. Kozuch and 1 other author(s). MICRO, page 185-197. ACM, (2013)Chapter Four - Simple Operations in Memory to Reduce Data Movement.V. Seshadri, and O. Mutlu. Advances in Computers, (2017)Aksharantar: Towards building open transliteration tools for the next billion users.Y. Madhani, S. Parthan, P. Bedekar, R. Khapra, V. Seshadri, A. Kunchukuttan, P. Kumar, and M. Khapra. CoRR, (2022)Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology.V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M. Kozuch, O. Mutlu, P. Gibbons, and T. Mowry. MICRO, page 273-287. ACM, (2017)BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling.L. Subramanian, D. Lee, V. Seshadri, H. Rastogi, and O. Mutlu. IEEE Trans. Parallel Distributed Syst., 27 (10): 3071-3087 (2016)Shiftry: RNN inference in 2KB of RAM.A. Kumar, V. Seshadri, and R. Sharma. Proc. ACM Program. Lang., 4 (OOPSLA): 182:1-182:30 (2020)RowClone: Accelerating Data Movement and Initialization Using DRAM.V. Seshadri, Y. Kim, C. Fallin, D. Lee, R. Ausavarungnirun, G. Pekhimenko, Y. Luo, O. Mutlu, P. Gibbons, M. Kozuch and 1 other author(s). CoRR, (2018)The Processing Using Memory Paradigm: In-DRAM Bulk Copy, Initialization, Bitwise AND and OR.V. Seshadri, and O. Mutlu. CoRR, (2016)

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Disambiguation of "Seshadri, Vivek"

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Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins.

Please choose a person to relate this publication to

Praveen Seshadri

Sangeetha Seshadri

Varadarajan Seshadri

Nagarajavel Vivekananthan

Vivek Venkataramani

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Seshadri, Vivek"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins.

Please choose a person to relate this publication to

Praveen Seshadri

Sangeetha Seshadri

Varadarajan Seshadri

Nagarajavel Vivekananthan

Vivek Venkataramani

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins.