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An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 1871-1879 (2012)A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology., , , , , , , , , и 9 other автор(ы). ISSCC, стр. 108-109. IEEE, (2023)Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (6): 474-478 (2007)An Injection-Locked Frequency Divider With Multiple Highly Nonlinear Injection Stages and Large Division Ratios., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 54-II (4): 313-317 (2007)3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS., , , , , , , и . ISSCC, стр. 1-3. IEEE, (2015)A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology., , , , , , , , , и 9 other автор(ы). IEEE J. Solid State Circuits, 59 (1): 8-18 (января 2024)A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS., , , , , , , , , и . IEEE J. Solid State Circuits, 50 (12): 3089-3100 (2015)A digital wideband CDR with ±15.6kppm frequency tracking at 8Gb/s in 40nm CMOS., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 442-444. IEEE, (2011)Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (9): 843-847 (2006)A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz., , , и . IEEE J. Solid State Circuits, 42 (3): 583-591 (2007)