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The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment., , , , , , and . Conf. Computing Frontiers, page 67-78. ACM, (2008)Hardware Transactional Memory with Operating System Support, HTMOS., , , and . Euro-Par Workshops, volume 4854 of Lecture Notes in Computer Science, page 8-17. Springer, (2007)Memory Controller for Vector Processor., , , , and . J. Signal Process. Syst., 90 (11): 1533-1549 (2018)Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core., , , , and . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)Hybrid Transactional Memory with Pessimistic Concurrency Control., , , , , , , and . Int. J. Parallel Program., 39 (3): 375-396 (2011)Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation., , and . CoRR, (2020)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , and . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)Improving the energy efficiency of hardware-assisted watchpoint systems., , , , and . DAC, page 54:1-54:6. ACM, (2013)System-level power estimation tool for embedded processor based platforms., , , , , and . RAPIDO, page 5:1-5:8. ACM, (2014)PaRV: Parallelizing Runtime Detection and Prevention of Concurrency Errors., , , , and . RV, volume 7687 of Lecture Notes in Computer Science, page 42-47. Springer, (2012)