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Disambiguation of "Peralías, Eduardo J."

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A 3.6mW @ 1.2V high linear 8th-order CMOS complex filter for IEEE 802.15.4 standard.

, , , and . ESSCIRC, page 99-102. IEEE, (2011)

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Eduardo Ospina

Eduardo Klein

Eduardo Monari

Eduardo Maurô

Eduardo Portabella

 

Other publications of authors with the same name

Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS., , and . SBCCI, page 21-26. ACM, (2007)INL systematic reduced-test technique for Pipeline ADCs., , and . ETS, page 1-6. IEEE, (2014)Structural testing of pipelined analog to digital converters., , and . ISCAS (1), page 436-439. IEEE, (2001)SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems., , , , and . DAC, page 281-286. ACM Press, (1997)Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy., , and . ISCAS, page 1-5. IEEE, (2020)Statistical behavioral modeling and characterization of A/D converters., , and . ICCAD, page 562-566. IEEE Computer Society / ACM, (1995)Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator., , , , , , and . ETS, page 1-6. IEEE, (2016)Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages., , and . SBCCI, page 317-322. IEEE Computer Society, (2003)Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach., , , and . ISCAS, page 1-5. IEEE, (2018)On-chip biased voltage-controlled oscillator with temperature compensation of the oscillation amplitude for robust I/Q generation., , , , and . ISCAS, page 1979-1982. IEEE, (2010)