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Disambiguation of "Tanigawa, Kazuya"

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A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks.

, , , , , and . IEICE Trans. Inf. Syst., 95-D (2): 324-334 (2012)

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Kazuya Yamashita

 

Other publications of authors with the same name

EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture., , , , , and . ReConFig, page 448-454. IEEE Computer Society, (2011)Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation., and . FPT, page 273-276. IEEE, (2008)Exploring compact design on high throughput coarse grained reconfigurable architectures., , , and . FPL, page 543-546. IEEE, (2008)A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 434-443. Springer, (2002)Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area., and . ISOCC, page 187-190. IEEE, (2011)Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor., , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 388-393. Springer, (2010)A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks., , , , , and . IEICE Trans. Inf. Syst., 95-D (2): 324-334 (2012)Design of superscalar processor with multi-bank register file., , , , , , , and . ISCAS (4), page 3507-3510. IEEE, (2005)Development of a Trax Artificial Intelligence algorithm using path and edge., , , , and . FPT, page 256-259. IEEE, (2015)A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism., , and . FPT, page 311-314. IEEE, (2003)