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Disambiguation of "Ikeda, Shoji"

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2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read.

, , , , , , , , , , , , , and . ISSCC, page 480-617. IEEE, (2007)

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Yukihiro Ikeda

Mitsuyoshi Ikeda

Rafael Shoji

Shoji Wada

Shingo Ikeda

 

Other publications of authors with the same name

Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits., , , , , , , , and . IEICE Trans. Electron., 93-C (5): 608-613 (2010)An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (2): 109-119 (2016)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme., , , , , , and . ASP-DAC, page 475-476. IEEE, (2012)Dependence of tunnel magnetoresistance on ferromagnetic electrode materials in MgO-barrier magnetic tunnel junctions, , , , and . Journal of Magnetism and Magnetic MaterialsVolume 310, (2007)Keywords: Tunnel magnetoresistance; MgO barrier; CoFeB.MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues., , , , , , and . DATE, page 433-435. IEEE, (2009)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz., , , , , , , , , and 6 other author(s). ISSCC, page 202-204. IEEE, (2019)2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read., , , , , , , , , and 4 other author(s). ISSCC, page 480-617. IEEE, (2007)A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture., , , , , , , and . VLSIC, page 44-45. IEEE, (2012)