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Modeling steep slope devices: From circuits to architectures., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Influence of compiler optimizations on system power., , , and . DAC, page 304-307. ACM, (2000)Design and analysis of an NoC architecture from performance, reliability and energy perspective., , , , and . ANCS, page 173-182. ACM, (2005)A low latency router supporting adaptivity for on-chip interconnects., , , , and . DAC, page 559-564. ACM, (2005)Design space exploration of workload-specific last-level caches., , , , and . ISLPED, page 243-248. ACM, (2012)Hardware and Software Techniques for Controlling DRAM Power Modes., , , , and . IEEE Trans. Computers, 50 (11): 1154-1173 (2001)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility., , , , , , , , , and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)Robust Coreset Construction for Distributed Machine Learning., , , , , and . IEEE J. Sel. Areas Commun., 38 (10): 2400-2417 (2020)Fine-to-Coarse Object Classification of Very Large Images., and . ICIP, page 3498-3502. IEEE, (2023)Leakage Energy Management in Cache Hierarchies., , , , , , and . IEEE PACT, page 131-140. IEEE Computer Society, (2002)