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Disambiguation of "Miura, Naoki"

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17.4 Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes.

, , , , , , , , , , , , , and . ISSCC, page 320-322. IEEE, (2024)

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Naotomo Miura

Naoki Yoshida

Kota Miura

Yuzuru Miura

Naoki Ueda

 

Other publications of authors with the same name

A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table., , , , , and . ISPACS, page 351-356. IEEE, (2015)Second-language Instinct and Instruction Effects: Nature and Nurture in Second-language Acquisition., , , , , , , , and . J. Cognitive Neuroscience, 23 (10): 2716-2730 (2011)A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS., , and . IEEE J. Solid State Circuits, 56 (2): 465-475 (2021)Effectiveness of SIEPON Package B Compliant ONU Sleep Technique and Impact on Latency and Transmission Efficiency from a Theoretical Point of View., , , , and . JOCN, 6 (4): 362-370 (2014)Cortical activation during reading of ancient versus modern Japanese texts: fMRI study., , , , , , , , , and 1 other author(s). NeuroImage, 26 (2): 426-431 (2005)Extendable point-to-multi-point protocol processor for 10G-EPON MAC SoCs., , , , , , and . ISCAS, page 1464-1467. IEEE, (2012)Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS., , , , , , and . IEICE Trans. Electron., 103-C (10): 489-496 (2020)A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS., , , , , , and . SoCC, page 150-154. IEEE, (2019)A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation., , , and . A-SSCC, page 239-242. IEEE, (2018)The human parietal cortex is involved in spatial processing of tongue movement - an fMRI study., , , , , , and . NeuroImage, 21 (4): 1289-1299 (2004)