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A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range., , , , , , and . ISSCC, page 1-3. IEEE, (2022)Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros., , , , , , , , , and 1 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1191-1205 (April 2024)Improving compute in-memory ECC reliability with successive correction., , , , , , , and . DAC, page 745-750. ACM, (2022)Neuromorphic Swarm on RRAM Compute-in-Memory Processor for Solving QUBO Problem., , , , , and . DAC, page 1-6. IEEE, (2023)A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems., , , , , , and . ISSCC, page 1-3. IEEE, (2022)Breaking Barriers: Maximizing Array Utilization for Compute in-Memory Fabrics., , , , , and . VLSI-SOC, page 123-128. IEEE, (2020)Merged Logic and Memory Fabrics for AI Workloads., , and . ASP-DAC, page 305-310. ACM, (2021)30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance., , , , , , , , , and 2 other author(s). ISSCC, page 482-484. IEEE, (2024)Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking., , , , , , and . ISCAS, page 1. IEEE, (2023)Automatic Generation of Translators for Packet-Based and Emerging Protocols., , and . ISQED, page 488-495. IEEE, (2021)