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The design of a latency constrained, power optimized NoC for a 4G SoC.

, , , and . NOCS, page 86. IEEE Computer Society, (2009)

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Capacity optimized NoC for multi-mode SoC., , , and . DAC, page 942-947. ACM, (2011)Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study., , , and . Low Power Networks-on-Chip, Springer, (2011)A Cost Effective Centralized Adaptive Routing for Networks-on-Chip., , , , and . DSD, page 39-46. IEEE Computer Society, (2011)The era of many-modules SoC: revisiting the NoC mapping problem., , , and . NoCArc@MICRO, page 43-48. ACM, (2009)Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study., , , and . DATE, page 1408-1413. IEEE Computer Society, (2010)BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP., , and . IEEE Comput. Archit. Lett., 7 (2): 61-64 (2008)Best of both worlds: A bus enhanced NoC (BENoC)., , , and . NOCS, page 173-182. IEEE Computer Society, (2009)Efficient link capacity and QoS design for network-on-chip., , , , , and . DATE, page 9-14. European Design and Automation Association, Leuven, Belgium, (2006)The design of a latency constrained, power optimized NoC for a 4G SoC., , , and . NOCS, page 86. IEEE Computer Society, (2009)Packet-level static timing analysis for NoCs., , , , and . NOCS, page 88. IEEE Computer Society, (2009)