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A 1.8-pJ/b, 12.5-25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit., , , , , , and . IEEE J. Solid State Circuits, 53 (2): 470-483 (2018)Efficient Parallelization of Polyphase Arbitrary Resampling FIR Filters for High-Speed Applications., , , , and . J. Signal Process. Syst., 90 (3): 295-303 (2018)DSP-free 52km-long dispersion uncompensated optical link employing a 40 Gb/s O-band silicon microring modulator assembled with a 1V-CMOS driver., , , , , , , , , and . OECC/PSC, page 1-3. IEEE, (2019)A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst Mode Applications in PONs., , , , , and . ECOC, page 1-3. IEEE, (2017)A DC-coupled 50 Gb/s 0.064 pJ/bit thin-oxide level shifter in 28 nm FDSOI CMOS., , , , , , and . IEICE Electron. Express, 15 (3): 20171085 (2018)A 6-bit 56-GSa/s DAC in 55 nm SiGe BiCMOS., , , , , , , and . BCICTS, page 1-4. IEEE, (2021)A 100-GS/s Four-to-One Analog Time Interleaver in 55-nm SiGe BiCMOS., , , , , , , and . IEEE J. Solid State Circuits, 56 (8): 2539-2549 (2021)56-Gb/s Silicon Optical Receiver Using a Low-Noise Fully-Differential Transimpedance Amplifier in SiGe SiCMOS., , , , , , , , and . ECOC, page 1-3. IEEE, (2018)Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s., , , , , , and . IEEE J. Solid State Circuits, 55 (7): 1935-1945 (2020)12.4 A 700mW 4-to-1 SiGe BiCMOS 100GS/s Analog Time-Interleaver., , , , , , , and . ISSCC, page 214-216. IEEE, (2020)