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Using Data Compression to Increase Energy Savings in Multi-bank Memories.

, , , and . Euro-Par, volume 3149 of Lecture Notes in Computer Science, page 310-317. Springer, (2004)

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The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense., , , , , and . IJDSN, 2 (3): 267-287 (2006)Leveraging value locality for efficient design of a hybrid cache in multicore processors., , , and . ICCAD, page 1-8. IEEE, (2017)Performance aware secure code partitioning., , and . DATE, page 1122-1127. EDA Consortium, San Jose, CA, USA, (2007)Memory bank aware dynamic loop scheduling., , , and . DATE, page 1671-1676. EDA Consortium, San Jose, CA, USA, (2007)Adaptive prefetching for shared cache based chip multiprocessors., , and . DATE, page 773-778. IEEE, (2009)Using data replication to reduce communication energy on chip multiprocessors., , , and . ASP-DAC, page 769-772. ACM Press, (2005)Optimizing embedded applications using programmer-inserted hints., and . ASP-DAC, page 157-160. ACM Press, (2005)FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads., , and . HPCA, page 426-439. IEEE, (2019)Soft errors issues in low-power caches., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1157-1166 (2005)Taking Garbage Collection Overheads Off the Critical Path in SSDs., , and . Middleware, volume 7662 of Lecture Notes in Computer Science, page 164-186. Springer, (2012)