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SYQ: Learning Symmetric Quantization for Efficient Deep Neural Networks.

, , , и . CVPR, стр. 4300-4309. Computer Vision Foundation / IEEE Computer Society, (2018)

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Irene Blottner

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Gerhard Blottner

Stefan Blöttner

Annemarie Blottner

 

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Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs., , , , , , , , , и 1 other автор(ы). CoRR, (2018)LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications., , , и . FPL, стр. 291-297. IEEE, (2020)DarwiNN: efficient distributed neuroevolution under communication constraints., , , и . GECCO Companion, стр. 141-142. ACM, (2020)Efficient Error-Tolerant Quantized Neural Network Accelerators., , , , , , и . DFT, стр. 1-6. IEEE, (2019)Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems., , и . FCCM, стр. 175-182. IEEE Computer Society, (2009)Corrigendum: Applications and techniques for fast machine learning in science., , , , , , , , , и 37 other автор(ы). Frontiers Big Data, (2024)QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware., , , и . ACM J. Emerg. Technol. Comput. Syst., 15 (4): 37:1-37:38 (2019)Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring., , и . LCTES, стр. 129-136. ACM, (2009)ACCL+: an FPGA-Based Collective Engine for Distributed Applications., , , , , , , и . OSDI, стр. 211-231. USENIX Association, (2024)Dataflow architectures for 10Gbps line-rate key-value-stores., и . Hot Chips Symposium, стр. 1-25. IEEE, (2013)