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Congestion estimation during top-down placement.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (1): 72-80 (2002)

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Routability driven white space allocation for fixed-die standard-cell placement., , and . ISPD, page 42-47. ACM, (2002)A mixed mean-value and crank-based model of a dual-stage turbocharged SI engine for Hardware-In-the-Loop simulation., and . ACC, page 3791-3796. IEEE, (2010)A Deep Hybrid Neural Network Forecasting for Multivariate Non-stationary Time Series., and . HCC, volume 12634 of Lecture Notes in Computer Science, page 184-190. Springer, (2020)Multi-center congestion estimation and minimization during placement., , , and . ISPD, page 147-152. ACM, (2000)A Standard-Cell Placement Tool for Designs with High Row Utilization., , and . ICCD, page 45-. IEEE Computer Society, (2002)Timing-driven placement using design hierarchy guided constraint generation., , and . ICCAD, page 177-180. ACM / IEEE Computer Society, (2002)Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs., , , and . Journal of Circuits, Systems, and Computers, 13 (1): 77-100 (2004)Dragon2006: blockage-aware congestion-controlling mixed-size placer., , , , and . ISPD, page 209-211. ACM, (2006)Congestion-Driven Physical Design., and . Handbook of Algorithms for Physical Design Automation, Auerbach Publications, (2008)Predicting potential performance for digital circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (3): 253-262 (2002)