( en | de | ru )

 

Disambiguation of "Kojima, Takuya"

Author of the publication

copydeleteadd this publication to your clipboard
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops.

, , , , , , , , and . MCSoC, page 273-280. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Takuya Soma

Tomoko Kojima

Hajime Kojima

Takuya Suzuki

Taka Bluhme-Kojima

 

Other publications of authors with the same name

A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (4): 532-542 (April 2023)An Architecture- Independent CGRA Compiler enabling OpenMP Applications., , , , and . IPDPS Workshops, page 631-638. IEEE, (2022)Situation-based Proactive Human-Robotic Systems Interaction and Collaboration in Future Convenience Stores., , , , , , and . SII, page 1417-1424. IEEE, (2024)Glitch-aware variable pipeline optimization for CGRAs., , , and . ReConFig, page 1-6. IEEE, (2017)Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process., , , , and . CANDAR Workshops, page 269-274. IEEE, (2019)Scalable deep neural network accelerator cores with cubic integration using through chip interface., , , , , , , and . ISOCC, page 155-156. IEEE, (2017)SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks., , , , , and . COOL CHIPS, page 1-6. IEEE, (2024)An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings., , and . PDP, page 1-9. IEEE, (2022)Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops., , , , , , , , and . MCSoC, page 273-280. IEEE, (2021)Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation., , , , , and . IPDPS Workshops, page 639-646. IEEE, (2022)