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Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors., , and . IOLTS, page 110-115. IEEE, (2015)Switch folding: network-on-chip routers with time-multiplexed output ports., , , and . DATE, page 344-349. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Network-on-Chip Architectures - A Holistic Design Exploration, , and . Lecture Notes in Electrical Engineering Springer, (2010)On the Effects of Process Variation in Network-on-Chip Architectures., , , , , , and . IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)Networks-on-Chip With Double-Data-Rate Links., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (12): 3103-3114 (2017)ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining., , , , and . CoRR, (2022)DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity., , , and . CoRR, (2024)Dynamic Adjustment of Test-Sequence Duration for Increasing the Functional Coverage., , , and . IVSW, page 61-66. IEEE, (2019)A High-Performance and Energy-Efficient Virtually Tagged Stack Cache Architecture for Multi-core Environments., , , and . HPCC, page 58-67. IEEE, (2011)2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)., , , , , , and . DFT, page 1-4. IEEE, (2020)