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Link pipelining strategies for an application-specific asynchronous NoC.

, , and . NOCS, page 185-192. ACM/IEEE Computer Society, (2011)

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A Novel Asynchronous Network-On-Chip Based on Source Asynchronous Signaling., , , and . ASYNC, page 71-77. IEEE, (2023)Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study., , and . VLSI-SoC, page 7-12. IEEE, (2010)Congruent Weak Conformance, a Partial Order among Processes., and . FORTE, volume 2529 of Lecture Notes in Computer Science, page 34-49. Springer, (2002)Automatic addition of reset in asynchronous sequential control circuits., and . VLSI-SoC, page 374-379. IEEE, (2013)A Design Space and its Patterns: Modelling 2phase Asynchronous Pipelines., and . HOWARD-60, volume 42 of EPiC Series in Computing, EasyChair, (2014)Automatic Timing Closure for Relative Timed Designs., and . VLSI-SOC, page 82-87. IEEE, (2020)Dynamic gates with hysteresis and configurable noise tolerance., and . VLSI-SoC, page 184-189. IEEE, (2007)Interfacing Synchronous and Asynchronous Domains for Open Core Protocol., , and . VLSID, page 282-287. IEEE Computer Society, (2014)Path Based Timing Validation for Timed Asynchronous Design., , and . VLSID, page 511-516. IEEE Computer Society, (2016)SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead., , and . ASYNC, page 107-114. IEEE Computer Society, (2013)