( en | de | ru )

 

Disambiguation of "OSHIMA, M."

Author of the publication

copydeleteadd this publication to your clipboard
Fibres optiques, technologie et applications pour les compagnies d'électricité Fibre optics, technology and applications in power industry

, , , , , , , , , and . (-)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tomoko Oshima-Takago

Simon M M Laimer

M. Biswas M. Dam

Marcel M M Kuypers

Bernhard M M Lang

 

Other publications of authors with the same name

Fibres optiques, technologie et applications pour les compagnies d'électricité Fibre optics, technology and applications in power industry, , , , , , , , , and . (-)Proceedings of the IAEA Technical Meeting in collaboration with NEA on Specific Applications of Research Reactors: Provision of Nuclear Data, , , , , and . Report, INDC(NDS)-0574. International Atomic Energy Agency, Vienna, Austria, (July 2010)A Pole Change Generator for Micro Windmill with Maximum Power Point Tracking System., , , , , , and . ISIC, page 640-645. IEEE, (2007)Importance of visualization in advancement of science and technology., and . J. Vis., 8 (4): 285 (2005)Fibres optiques, technologie et applications pour les compagnies d'électricité Fibre optics, technology and applications in power industry, , , , , and . Electra, (-)Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors., , , , , , , , , and 3 other author(s). A-SSCC, page 133-136. IEEE, (2011)Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links., , , , , , , , , and 3 other author(s). CICC, page 605-608. IEEE, (2009)A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O., , , , , , , , , and . ISSCC, page 246-247. IEEE, (2010)A Versatile 90-nm CMOS Charge-Pump PLL for SerDes Transmitter Clocking., , , , , , and . IEEE J. Solid State Circuits, 41 (8): 1894-1907 (2006)A versatile low-jitter PLL in 90-nm CMOS for SerDes transmitter clocking., , , , , , , , , and 10 other author(s). CICC, page 553-556. IEEE, (2005)