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Disambiguation of "Takata, Hidehiro"

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On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch.

, , , , , and . IEICE Trans. Electron., 94-C (4): 511-519 (2011)

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On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure., , , , , and . ESSCIRC, page 183-186. IEEE, (2011)Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs., , , , , , , and . ISSCC, page 288-603. IEEE, (2007)Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 15 (2): 17:1-17:17 (2010)Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling., , , , , , and . DAC, page 884-889. ACM, (2008)Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations., , , , and . IEICE Trans. Electron., 92-C (4): 475-482 (2009)Decoupling capacitance boosting for on-chip resonant supply noise reduction., , , , , and . DDECS, page 111-114. IEEE Computer Society, (2011)Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (12): 918-921 (2012)Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation., , , , , and . IEICE Trans. Electron., 95-C (4): 586-593 (2012)Misleading energy and performance claims in sub/near threshold digital systems., , , , , , , , , and 1 other author(s). ICCAD, page 625-631. IEEE, (2010)A Data-Driven Architecture for Distributed Parallel Processing., , , , , , , , and . ICCD, page 218-224. IEEE Computer Society, (1991)