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Disambiguation of "De, Vivek"

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Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.

, , , , , and . ITC, page 1051-1059. IEEE Computer Society, (2000)

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Nagarajavel Vivekananthan

Vivek Venkataramani

Vivek Ramamurthy

Vivek Shetty

Vivek Bose

 

Other publications of authors with the same name

Reducing the data switching activity of serialized datastreams., , , and . ISCAS, IEEE, (2006)Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications., , , , and . DAC, page 430-435. ACM Press, (1999)F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems., , , , , and . ISSCC, page 506-508. IEEE, (2017)Near-threshold voltage design in nanoscale CMOS.. DATE, page 612. EDA Consortium San Jose, CA, USA / ACM DL, (2013)On-Die Supply-Resonance Suppression Using Band-Limited Active Damping., , , , , , , , , and 1 other author(s). ISSCC, page 286-603. IEEE, (2007)Variation-tolerant circuits: circuit solutions and techniques., , and . DAC, page 762-763. ACM, (2005)Comparative Analysis of Conventional and Statistical Design Techniques., , , , , and . DAC, page 238-243. IEEE, (2007)A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging., , , , , , and . IEEE J. Solid State Circuits, 51 (1): 117-129 (2016)A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 53 (1): 8-19 (2018)Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits., and . IEEE J. Solid State Circuits, 48 (4): 895-896 (2013)