( en | de | ru )

 

Disambiguation of "Shirinzadeh, Saeideh"

Author of the publication

copydeleteadd this publication to your clipboard
Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars.

, , and . ISCAS, page 1-5. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Saeideh Ebadi

Saeideh Mohammadzadeh

Saeideh Edalati Boostan

 

Other publications of authors with the same name

High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design., and . J. Electron. Test., 29 (4): 537-544 (2013)An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization., , , and . GECCO, page 1232-1239. ACM, (2017)Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications., , , , , and . VLSI-SoC, page 1-6. IEEE, (2022)Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles., , , , and . DSD, page 793-800. IEEE, (2022)Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars., , , , and . ASP-DAC, page 19-25. ACM, (2023)Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm., , , and . GECCO (Companion), page 79-80. ACM, (2016)Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars., , and . ISCAS, page 1-5. IEEE, (2020)Parallel Computing of Graph-based Functions in ReRAM., , and . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 41:1-41:24 (2022)Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits., , and . ISVLSI, page 431-436. IEEE, (2019)Synthesis and optimization for logic-in-memory computing using memristive devices.. University of Bremen, Germany, (2018)