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Disambiguation of "Huang, Ru"

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Khronos: Fusing Memory Access for Improved Hardware RTL Simulation.

, , , , and . MICRO, page 180-193. ACM, (2023)

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Ru-Jin Huang

Ru Zhang

Ru Xie

Tomasz Ru

Ru Hao

 

Other publications of authors with the same name

Heterogeneous integration of nano enabling devices for 3D ICs., , , , , , , , , and 7 other author(s). ISLPED, page 249-254. IEEE, (2013)Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (2): 703-716 (February 2024)TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (8): 3377-3387 (2021)Time Complexity of In-Memory Matrix-Vector Multiplication., and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (8): 2785-2789 (2021)Hadamard product-based in-memory computing design for floating point neural network training., , , , , , , , , and . Neuromorph. Comput. Eng., 3 (1): 14009 (March 2023)Interactive Analog Layout Editing With Instant Placement and Routing Legalization., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (3): 698-711 (March 2023)Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (5): 1511-1524 (May 2024)CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 5034-5047 (December 2023)AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4139-4151 (November 2023)Statistical Compact Modeling With Artificial Neural Networks., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 5156-5160 (December 2023)