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Automatic generation of loop scheduling for VLIW., , , и . PACT, стр. 306-309. IFIP Working Group on Algol / ACM, (1995)Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core., , , , и . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , и . Int. J. Parallel Program., 32 (6): 447-474 (2004)Hybrid Transactional Memory with Pessimistic Concurrency Control., , , , , , , и . Int. J. Parallel Program., 39 (3): 375-396 (2011)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , и . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)Dynamic Cache Partitioning Based on the MLP of Cache Misses., , , и . Trans. High Perform. Embed. Archit. Compil., (2011)Errata on "Measuring Experimental Error in Microprocessor Simulation"., , , , , , и . SIGARCH Comput. Archit. News, 30 (1): 2-4 (2002)Partitioning: An Essential Step in Mapping Algorithms Into Systolic Array Processors., , и . Computer, 20 (7): 77-89 (1987)Register Constrained Modulo Scheduling., , , и . IEEE Trans. Parallel Distributed Syst., 15 (5): 417-430 (2004)CPU Accounting in CMP Processors., , , , , и . IEEE Comput. Archit. Lett., 8 (1): 17-20 (2009)