( en | de | ru )

 

Disambiguation of "Valero, Mateo"

Author of the publication

copydeleteadd this publication to your clipboard
Dynamic transaction coalescing.

, , , , , , and . Conf. Computing Frontiers, page 18:1-18:10. ACM, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ana Maria Mateo Rosell

Carlos Mateo Balmelli

Mateo Hermel

Silvia Valero

Alejandro Valero

 

Other publications of authors with the same name

Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Topic 15+20: Multimedia and Embedded Systems., , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 651-652. Springer, (2001)Parallel Computer Architecture., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 537-538. Springer, (2000)Memory Access Synchronization in Vector Multiprocessors., , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 414-425. Springer, (1994)Exploiting instruction- and data-level parallelism., and . IEEE Micro, 17 (5): 20-27 (1997)Multicore: The View from Europe., and . IEEE Micro, 30 (5): 2-4 (2010)Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors., , and . IEEE Trans. Computers, 31 (12): 1227-1234 (1982)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)