( en | de | ru )

 

Disambiguation of "Valero, Mateo"

Author of the publication

copydeleteadd this publication to your clipboard
Dynamic transaction coalescing.

, , , , , , and . Conf. Computing Frontiers, page 18:1-18:10. ACM, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ana Maria Mateo Rosell

Carlos Mateo Balmelli

Mateo Hermel

Silvia Valero

Alejandro Valero

 

Other publications of authors with the same name

Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)Access to streams in multiprocessor systems., , and . PDP, page 310-316. IEEE, (1993)A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)Picos: A hardware runtime architecture support for OmpSs., , , , and . Future Gener. Comput. Syst., (2015)Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , and . Int. J. Parallel Program., 32 (6): 447-474 (2004)Hybrid Transactional Memory with Pessimistic Concurrency Control., , , , , , , and . Int. J. Parallel Program., 39 (3): 375-396 (2011)Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core., , , , and . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)