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Disambiguation of "Chi, Hsin-Chou"

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Design of timing-error-resilient systolic arrays for matrix multiplication.

, , and . ISOCC, page 219-222. IEEE, (2011)

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Hsin Chou

Hsin Chi

Chi-Chou Yeh

Hsin-Chi Kuan

Chi-Wu Chou

 

Other publications of authors with the same name

Efficient Switches for Network-on-Chip Based Embedded Systems., and . EUC, volume 3824 of Lecture Notes in Computer Science, page 67-76. Springer, (2005)Area Utilization Based Mapping for Network-on-chip Architectures with Over-sized IP Cores., , and . HPCC-ICESS, page 1520-1525. IEEE Computer Society, (2012)Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures., , and . DELTA, page 415-420. IEEE Computer Society, (2008)Routing Tree Construction for Interconnection Network with Irregular Topologies., and . PDP, page 157-164. IEEE Computer Society, (2003)Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers., and . ICCD, page 233-238. IEEE Computer Society, (1991)Design of a Reconfigurable Pipelined Switch for Faulty On-Chip Networks., , and . SIES, page 51-56. IEEE, (2010)A Deadlock-Free Routing Scheme for Interconnection Networks with Irregular Topologies., and . ICPADS, page 88-95. IEEE Computer Society, (1997)Efficient diagnosable design of the IEEE P1500 architecture for SoC testing., , and . NESEA, page 1-7. IEEE Computer Society, (2011)A high-performance VLSI architecture for variable block size motion estimation., , and . GCCE, page 123-124. IEEE, (2014)Efficient diagnosis of scan chains with single stuck-at faults., , and . CISS, page 473-476. IEEE, (2009)