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Disambiguation of "Piccolboni, Luca"

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Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.

, , , , , , , , , , , , , , and . FMCAD, page 42-52. IEEE, (2021)

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Luca Rizzini

Luca Tranchini

Luca Tuninetti

Alfonz Luca

Luca Criscuolo

 

Other publications of authors with the same name

MasterMind: Many-Accelerator SoC Architecture for Real-Time Brain-Computer Interfaces., , , and . ICCD, page 101-108. IEEE, (2021)Broadening the exploration of the accelerator design space in embedded scalable platforms., , , and . HPEC, page 1-7. IEEE, (2017)Simplified stimuli generation for scenario and assertion based verification., and . LATW, page 1-6. IEEE, (2014)Stimuli generation through invariant mining for black-box verification., and . VLSI-SoC, page 1-6. IEEE, (2016)14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration., , , , , , , , , and 19 other author(s). ISSCC, page 262-264. IEEE, (2024)An Analysis of Accelerator Data-Transfer Modes in NoC-Based SoC Architectures., , , and . HPEC, page 1-7. IEEE, (2023)Teaching Heterogeneous Computing with System-Level Design Methods., , , , , , , and . WCAE@ISCA, page 4:1-4:8. ACM, (2019)KAIROS: Incremental Verification in High-Level Synthesis through Latency-Insensitive Design., , and . FMCAD, page 105-109. IEEE, (2019)HARDROID: Transparent Integration of Crypto Accelerators in Android., , , and . HPEC, page 1-8. IEEE, (2021)COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators., , , and . CoRR, (2019)