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A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 34 (11): 1580-1588 (1999)An approach for multilevel logic cell optimization in module generators., and . Great Lakes Symposium on VLSI, page 284-289. IEEE, (1991)A 286 mm2 256 Mb DRAM with ×32 both-ends DQ., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 31 (4): 567-574 (1996)A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (12): 1970-1979 (December 2023)High-level synthesis transformations for programmable architectures., , and . EURO-DAC, page 8-13. IEEE Computer Society, (1993)A CAD tool for designing large, fault-tolerant VLSI arrays., , and . Great Lakes Symposium on VLSI, page 132-137. IEEE, (1991)A New Approach for Designing Fault-Tolerant Array Processors., and . Fault-Tolerant Computing Systems, volume 283 of Informatik-Fachberichte, page 324-331. Springer, (1991)Fault-tolerant designs for 256 Mb DRAM., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 31 (4): 558-566 (1996)An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (12): 5182-5192 (2022)