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Performance Evaluation of Compiler Controlled Power Saving Scheme., , , , , , , and . ISHPC, volume 4759 of Lecture Notes in Computer Science, page 480-493. Springer, (2005)Flexible test mode approach for 256-Mb DRAM., , , , , , , , , and . IEEE J. Solid State Circuits, 32 (10): 1525-1534 (1997)Fault-tolerant designs for 256 Mb DRAM., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 31 (4): 558-566 (1996)A 286 mm2 256 Mb DRAM with ×32 both-ends DQ., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 31 (4): 567-574 (1996)