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Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip.

P. Rantala, T. Lehtonen, J. Isoaho, and J. Plosila. SoC, page 1-4. IEEE, (2006)

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Martin Juha

Juha Tiihonen

Attila Juhász

Ingolf Juhasz-Böss

Juha Reunanen

Other publications of authors with the same name

Efficient application mapping in resource limited homogeneous NoC-based manycore systems.G. Georgakarakos, M. Daneshtalab, and J. Plosila. HPCS, page 207-212. IEEE, (2013)Design space exploration of thermal-aware many-core systems.K. Vaddina, A. Rahmani, M. Fattah, P. Liljeberg, and J. Plosila. J. Syst. Archit., 59 (10-D): 1197-1213 (2013)Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study.L. Guang, E. Nigussie, J. Plosila, and H. Tenhunen. Int. J. Adapt. Resilient Auton. Syst., 3 (3): 72-91 (2012)HIBS - Novel inter-layer bus structure for stacked architectures.M. Daneshtalab, M. Ebrahimi, and J. Plosila. 3DIC, page 1-7. IEEE, (2011)High-performance on-chip network platform for memory-on-processor architectures.M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen. ReCoSoC, page 1-6. IEEE, (2011)Energy-Efficient Navigation of an Autonomous Swarm with Adaptive Consciousness.J. Yasin, H. Mahboob, M. Haghbayan, M. Yasin, and J. Plosila. Remote. Sens., 13 (6): 1059 (2021)Parallel imperialist competitive algorithms.A. Majd, G. Sahebi, M. Daneshtalab, J. Plosila, S. Lotfi, and H. Tenhunen. Concurr. Comput. Pract. Exp., (2018)Memory-Efficient On-Chip Network With Adaptive Interfaces.M. Daneshtalab, M. Ebrahimi, P. Liljeberg, J. Plosila, and H. Tenhunen. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (1): 146-159 (2012)Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip.A. Rahmani, K. Vaddina, K. Latif, P. Liljeberg, J. Plosila, and H. Tenhunen. IET Circuits Devices Syst., 6 (5): 308-321 (2012)Boosting performance of self-timed delay-insensitive bit parallel on-chip interconnects.E. Nigussie, S. Tuuna, J. Plosila, P. Liljeberg, J. Isoaho, and H. Tenhunen. IET Circuits Devices Syst., 5 (6): 505-517 (2011)

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Disambiguation of "Plosila, Juha"

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Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip.

Please choose a person to relate this publication to

Martin Juha

Juha Tiihonen

Attila Juhász

Ingolf Juhasz-Böss

Juha Reunanen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Plosila, Juha"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip.

Please choose a person to relate this publication to

Martin Juha

Juha Tiihonen

Attila Juhász

Ingolf Juhasz-Böss

Juha Reunanen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Fault-tolerant Routing Approach for Reconfigurable Networks-on-Chip.