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CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits., , , , , , , and . ASP-DAC, page 336-343. IEEE, (2011)Analog performance of strained SOI nanowires down to 10K., , , , , , and . ESSDERC, page 222-225. IEEE, (2016)Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below., , , , , , , , , and 21 other author(s). ESSCIRC, page 88-91. IEEE, (2009)Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs., , , , , and . ICICDT, page 1-4. IEEE, (2014)Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities., , , , , , , , , and 6 other author(s). ESSDERC, page 121-124. IEEE, (2012)Multibranch mobility characterization: Evidence of carrier mobility enhancement by back-gate biasing in FD-SOI MOSFET., , , , , , , , and . ESSDERC, page 209-212. IEEE, (2012)3D monolithic integration., , , , , , , , , and 6 other author(s). ISCAS, page 2233-2236. IEEE, (2011)Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors., , , , , and . ESSDERC, page 223-226. IEEE, (2021)Opportunities brought by sequential 3D CoolCube™ integration., , , , , , , , , and 11 other author(s). ESSDERC, page 226-229. IEEE, (2016)Effect of measurement speed (μs-800 ps) on the characterization of reliability behaviors for FDSOI nMOSFETs., , , , , , , , and . IRPS, page 6. IEEE, (2018)