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An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS., , , , , , , , , и 1 other автор(ы). VLSIC, стр. 176-177. IEEE, (2012)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications., , , , , , и . ISSCC, стр. 94-95. IEEE, (2009)A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 55 (6): 1516-1529 (2020)Design of wide-band CMOS VCO for multiband wireless LAN applications., , , , , , и . IEEE J. Solid State Circuits, 38 (8): 1333-1342 (2003)A low-voltage multi-GHz VCO with 58% tuning range in SOI CMOS., , , , , , и . CICC, стр. 423-426. IEEE, (2002)Cryogenic CMOS: design considerations for future quantum computing systems., , , , , , , , , и 4 other автор(ы). CICC, стр. 1-8. IEEE, (2023)A 4GS/s, 8.45 ENOB and 5.7fJ/conversion, digital assisted, sampling system in 45nm CMOS SOI., , и . CICC, стр. 1-4. IEEE, (2011)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion., , , , , , , , , и 4 other автор(ы). CICC, стр. 1-4. IEEE, (2013)An ultra-high bandwidth sub-ranging ADC with programmable dynamic range in 32nm CMOS SOI., , и . MWSCAS, стр. 448-451. IEEE, (2017)