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Disambiguation of "Ferriss, Mark A."

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An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)

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Mark A Nusselein

Mark A Awabdy

Mark A Nusselein

Mark Yampolsky

Maßnahmen zur Sicherung von E2E-QoS bei verketteten Diensten. Uni München, (2009)

Mark Schütte

Crf2 - ein neues Antigen von Aspergillus fumigatus. TU Braunschweig, (2009)
 

Other publications of authors with the same name

A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme., and . IEEE J. Solid State Circuits, 43 (11): 2464-2471 (2008)A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (6): 1516-1529 (2020)A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS., , , , , , , , , and 5 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (8): 2009-2017 (2013)A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 52 (12): 3373-3391 (2017)10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs., , , , and . ISSCC, page 196-198. IEEE, (2016)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion., , , , , , , , , and 4 other author(s). CICC, page 1-4. IEEE, (2013)A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance., , and . IEEE J. Solid State Circuits, 50 (5): 1214-1223 (2015)An Integral Path Self-Calibration Scheme for a Dual-Loop PLL., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 48 (4): 996-1008 (2013)Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits., , , , , , , , , and 4 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2243-2252 (2014)An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS., , , , , , , , , and 1 other author(s). VLSIC, page 176-177. IEEE, (2012)