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Larrabee: a many-core Intel architecture for visual computing.. Conf. Computing Frontiers, page 225. ACM, (2009)MultPIM: Fast Stateful Multiplication for Processing-in-Memory., , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1647-1651 (2022)Micro-operation cache: a power aware frontend for variable instruction length ISA., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 801-811 (2003)Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture., , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (6): 474-478 (2009)PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics., , , and . CoRR, (2022)eXtended Block Cache., , , , , and . HPCA, page 61-70. IEEE Computer Society, (2000)Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory., , and . SOCC, page 1-6. IEEE, (2023)CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit., , , , and . ICCAD, page 150:1-150:9. IEEE, (2020)The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm., , , and . CoRR, (2019)FiltPIM: In-Memory Filter for DNA Sequencing., , , , , and . ICECS, page 1-4. IEEE, (2021)