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Disambiguation of "Matsuzawa, Akira"

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Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process.

, , , , , , , and . ESSDERC, page 254-257. IEEE, (2015)

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Akira Hayashima

Akira Hori

Akira Satake

Akira Yasui

Akira Hayashima

 

Other publications of authors with the same name

Feedforward compensation technique for all digital phase locked loop based synthesizers., , and . ISCAS, IEEE, (2006)A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (2): 422-433 (2013)A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs., , and . IEICE Trans. Electron., 96-C (4): 577-585 (2013)A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits., , , and . ASP-DAC, page 25-26. IEEE, (2014)A tail-current modulated VCO with adaptive-bias scheme., , , and . ASP-DAC, page 36-37. IEEE, (2015)A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique., , , , , and . ASP-DAC, page 5-6. IEEE, (2016)An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation., , , , , , and . ASP-DAC, page 13-14. IEEE, (2017)A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular., , , , , , , and . ESSCIRC, page 76-79. IEEE, (2015)19.5 An HCI-healing 60GHz CMOS transceiver., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS., , , , , , and . ISSCC, page 246-248. IEEE, (2018)