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Disambiguation of "Jeong, Deog-Kyoon"

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Multi-gigabit-rate clock and data recovery based on blind oversampling.

, and . IEEE Communications Magazine, 41 (12): 68-74 (2003)

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Su-Jeong Jeong

Wonrae Jeong

Hyung-Gon Jeong

Hang-Kyun Jeong

Chang-Kyo Jeong

 

Other publications of authors with the same name

A theoretical analysis of phase shift in pulse injection-locked oscillators., , , , , and . ISCAS, page 1662-1665. IEEE, (2016)A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop., , , , and . A-SSCC, page 73-76. IEEE, (2018)A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control., , and . CICC, page 1-4. IEEE, (2017)V-P cache: a storage efficient virtual cache organization., , , , and . Microprocess. Microsystems, 17 (9): 537-546 (1993)A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS., , and . ISCAS, page 1869-1872. IEEE, (2014)A Practical Implementation of IEEE 1588-2008 Transparent Clock for Distributed Measurement and Control Systems., and . IEEE Trans. Instrumentation and Measurement, 59 (2): 433-439 (2010)Virtual minimum potential queuing., , and . J. High Speed Networks, 16 (4): 323-339 (2007)A 10 Gb/s voltage swing level controlled output driver in 65-nm CMOS technology., and . ISOCC, page 53-56. IEEE, (2012)A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS., , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (10): 1834-1838 (2020)A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (9): 1569-1573 (2020)