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Disambiguation of "Khwa, Win-San"

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29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification.

, , , , , and . ISSCC, page 404-406. IEEE, (2021)

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San San Lin

San San Hmwe

Abdul Hamied Khwaja

Thein Win

Zaw Win

 

Other publications of authors with the same name

Circuit design for beyond von Neumann applications using emerging memory: From nonvolatile logics to neuromorphic computing., , , , , , , , , and . ISQED, page 23-28. IEEE, (2017)A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection., , , , , and . IEEE J. Solid State Circuits, 57 (1): 68-79 (2022)A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding., , , , , and . IEEE J. Solid State Circuits, 57 (3): 845-857 (2022)A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices., , , , , , , , , and 8 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices., , , , , , , , , and 4 other author(s). ISSCC, page 1-3. IEEE, (2022)34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices., , , , , , , , , and 5 other author(s). ISSCC, page 568-570. IEEE, (2024)29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification., , , , , and . ISSCC, page 404-406. IEEE, (2021)8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 58 (1): 303-315 (2023)A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS., , , , , , , , , and 3 other author(s). VLSI Circuits, page 120-. IEEE, (2019)High-density analog image storage in an analog-valued non-volatile memory array., , , , , , and . Neuromorph. Comput. Eng., 2 (4): 44018 (December 2022)