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Disambiguation of "Sun, Guangyu"

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Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design.

, , , , , and . ASAP, page 157-164. IEEE, (2019)

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Guangyu Wang

Guangyu Zhou

Guangyu Fu

Guangyu Wang

Guangyu Zhu

 

Other publications of authors with the same name

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (5): 629-638 (2016)GNNSampler: Bridging the Gap Between Sampling Algorithms of GNN and Hardware., , , , , , , and . ECML/PKDD (5), volume 13717 of Lecture Notes in Computer Science, page 498-514. Springer, (2022)Exploring Memory Hierarchy Design with Emerging Memory Technologies. Lecture Notes in Electrical Engineering Springer, (2014)Asymmetric-access aware optimization for STT-RAM caches with process variations., , , , and . ACM Great Lakes Symposium on VLSI, page 143-148. ACM, (2013)A frequent-value based PRAM memory architecture., , , and . ASP-DAC, page 211-216. IEEE, (2011)EdgeFlow: Open-Source Multi-layer Data Flow Processing in Edge Computing for 5G and Beyond., , , , and . CoRR, (2018)Rapid design space exploration of two-level unified caches., , , and . ISCAS, page 1937-1940. IEEE, (2014)Accelerate context switch by racetrack-SRAM hybrid cells., , and . NANOARCH, page 115-116. ACM, (2016)The Case for FPGA-Based Edge Computing., , , , , , and . IEEE Trans. Mob. Comput., 21 (7): 2610-2619 (2022)Stability Analysis Method for Three-Phase Multi-Functional Grid-Connected Inverters With Unbalanced Local Loads Considering the Active Imbalance Compensation., , , , and . IEEE Access, (2018)