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Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.

P. Edavoor, A. Raveendran, D. Selvakumar, V. Desalphine, S. Dharani, and G. Raut. VLSID, page 252-257. IEEE, (2023)

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Vivian Stoboy

Vivian Mast

Vivian Frank

Vivian Tini

Vivian Asante

Other publications of authors with the same name

Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA.V. Desalphine, S. Dashora, L. Mali, S. K, A. Raveendran, and D. Selvakumar. VDAT, page 1-4. IEEE, (2020)Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU.A. Raveendran, V. Kumar, V. Desalphine, and D. Selvakumar. VDAT, volume 1066 of Communications in Computer and Information Science, page 496-509. Springer, (2019)PositGen-A Verification Suite for Posit Arithmetic.A. Kulkarni, S. Pattanshetty, A. Raveendran, D. Selvakumar, S. Jean, and V. Desalphine. VLSID, page 204-209. IEEE, (2021)RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor.A. Raveendran, S. Jean, J. Mervin, V. Desalphine, and A. Selvakumar. VDAT, volume 1066 of Communications in Computer and Information Science, page 482-495. Springer, (2019)Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.P. Edavoor, A. Raveendran, D. Selvakumar, V. Desalphine, S. Dharani, and G. Raut. VLSID, page 252-257. IEEE, (2023)RISC-V out-of-order data conversion co-processor.A. Raveendran, V. Patil, V. Desalphine, P. Sobha, and A. Selvakumar. VDAT, page 1-2. IEEE Computer Society, (2015)Formal Verification and Analysis of a Pseudo Random Number Generator.D. Selvakumar, J. Mervin, S. Pattanshetty, and V. Desalphine. VDAT, page 1-6. IEEE, (2021)Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus.V. Kolagatla, V. Desalphine, and D. Selvakumar. VDAT, page 1-4. IEEE, (2021)A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture.A. Raveendran, S. Jean, J. Mervin, V. Desalphine, and D. Selvakumar. VLSID, page 207-212. IEEE, (2020)P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor.S. Jean, A. Raveendran, A. Selvakumar, G. Kaur, S. Dharani, S. Pattanshetty, and V. Desalphine. VLSID, page 282-287. IEEE, (2021)

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Disambiguation of "Desalphine, Vivian"

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Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.

Please choose a person to relate this publication to

Vivian Stoboy

Vivian Mast

Vivian Frank

Vivian Tini

Vivian Asante

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Desalphine, Vivian"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.

Please choose a person to relate this publication to

Vivian Stoboy

Vivian Mast

Vivian Frank

Vivian Tini

Vivian Asante

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Design and Analysis of Posit Quire Processing Engine for Neural Network Applications.