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Disambiguation of "Poulton, John W."

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A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors.

, , , , , and . CICC, page 1-4. IEEE, (2017)

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John W Yates

W Müller

W Löwa

W Voigt

W Warsch

 

Other publications of authors with the same name

A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs., , , , and . ISQED, page 1-8. IEEE, (2014)A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 154-155. IEEE, (2022)A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications., , , , , , , and . IEEE J. Solid State Circuits, 48 (12): 3206-3218 (2013)The design of DNA self-assembled computing circuitry., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 12 (11): 1214-1220 (2004)A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications., , , , , , and . ISSCC, page 404-405. IEEE, (2013)A 25 Gb/s 470 μW active inductor equalizer for ground referenced signaling receivers., , , , and . ISCAS, page 1-4. IEEE, (2017)A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensors., , , , , and . CICC, page 1-4. IEEE, (2017)CMOS High-Speed I/Os - Present and Future., , , , , , and . ICCD, page 454-461. IEEE Computer Society, (2003)8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring., , , , , , , and . ISSCC, page 156-157. IEEE, (2016)6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links., , , , , , , , , and 1 other author(s). ISSCC, page 126-128. IEEE, (2020)