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Quasi-static Scheduling for Concurrent Architectures., , , , and . Fundam. Informaticae, 62 (2): 171-196 (2004)A region-based theory for state assignment in speed-independent circuits., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (8): 793-812 (1997)Incremental high-level synthesis., , , , , , and . ASP-DAC, page 701-706. IEEE, (2010)A Framework for Modeling, Simulation and Automatic Code Generation of Sensor Network Application., , , , and . SECON, page 515-522. IEEE, (2008)Wireless Sensor Networks., and . Handbook of Hardware/Software Codesign, (2017)Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool., , , and . DAC, page 254-260. ACM Press, (1995)Solving the State Assignment Problem for Signal Transition Graphs., , , and . DAC, page 568-572. IEEE Computer Society Press, (1992)Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis., , , and . IEEE Access, (2017)Testing redundant asynchronous circuits by variable phase splitting., , and . EURO-DAC, page 328-333. IEEE Computer Society, (1994)Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework., , , and . J. Electronic Imaging, 23 (5): 053012 (2014)