( en | de | ru )

 

Disambiguation of "Calazans, Ney Laert Vilar"

Author of the publication

copydeleteadd this publication to your clipboard
From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.

, , , , , and . SBCCI, page 355-. IEEE Computer Society, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Loreto Vilar

Ignazio Vilardi

Fabio Vilardi

Sisi Alexandra Vilardi

David Vilar Torres

 

Other publications of authors with the same name

Evaluating the scalability of test buses., , , , , and . ISSoC, page 1-6. IEEE, (2013)A processor for IoT applications: An assessment of design space and trade-offs., , , , and . Microprocess. Microsystems, (2016)A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits., , , , and . ACM J. Emerg. Technol. Comput. Syst., 13 (2): 15:1-15:23 (2016)Requirements, Primitives and Models for Systems Specification., , and . SBCCI, page 323-330. IEEE Computer Society, (2002)Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits., , , , , and . VLSID, page 321-326. IEEE Computer Society, (2015)Leveraging QDI Robustness to Simplify the Design of IoT Circuits., , , , and . ISCAS, page 1-5. IEEE, (2020)Static Differential NCL Gates: Toward Low Power., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 62-II (6): 563-567 (2015)XGT4: An industrial grade, open source tester for multi-gigabit networks., , , , and . ICECS, page 252-255. IEEE, (2017)A generic FPGA emulation framework., , , , , , , and . ICECS, page 233-236. IEEE, (2012)A path towards average-case silicon via asynchronous resilient bundled-data design., and . ECCTD, page 1-4. IEEE, (2015)