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Disambiguation of "Moreno, Edson I."

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From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.

, , , , , and . SBCCI, page 355-. IEEE Computer Society, (2003)

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Edson Borin

Edson Wendland

Edson Murakami

Eduardo Moreno

Carlos Moreno

 

Other publications of authors with the same name

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture, , , and . CoRR, (2007)MoNoC: A monitored network on chip with path adaptation mechanism., , , , and . J. Syst. Archit., 60 (10): 783-795 (2014)Determining the test sources/sinks for NoC TAMs., , , and . ISVLSI, page 8-13. IEEE Computer Socity, (2013)A monitored NoC with runtime path adaptation., , , , and . ISCAS, page 1965-1968. IEEE, (2014)CAFES: A framework for intrachip application modeling and communication architecture design., , , , , and . J. Parallel Distributed Comput., 71 (5): 714-728 (2011)From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study., , , , , and . SBCCI, page 355-. IEEE Computer Society, (2003)Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture., , , and . DATE, page 62-63. IEEE Computer Society, (2005)Arbitration and routing impact on NoC design., , , and . International Symposium on Rapid System Prototyping, page 193-198. IEEE, (2011)Buffer depth and traffic influence on 3D NoCs performance., , , , , and . RSP, page 9-15. IEEE, (2012)Topological impact on latency and throughput: 2D versus 3D NoC comparison., , , , , and . SBCCI, page 1-6. IEEE, (2012)