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APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors.

Z. Xie, X. Xu, M. Walker, J. Knebel, K. Palaniswamy, N. Hebert, J. Hu, H. Yang, Y. Chen, and S. Das. MICRO, page 1-14. ACM, (2021)

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Qian Xie

Zhenwei Xie

Lan Xie

Jian Xie

Yangpei Xie

Other publications of authors with the same name

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model.Y. Lu, S. Liu, Q. Zhang, and Z. Xie. CoRR, (2023)The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.L. Chen, Y. Chen, Z. Chu, W. Fang, T. Ho, Y. Huang, S. Khan, M. Li, X. Li, Y. Liang and 24 other author(s). CoRR, (2024)Robustify ML-Based Lithography Hotspot Detectors.J. Pan, C. Chang, Z. Xie, J. Hu, and Y. Chen. ICCAD, page 134:1-134:7. ACM, (2022)RouteNet: routability prediction for mixed-size designs using convolutional neural network.Z. Xie, Y. Huang, G. Fang, H. Ren, S. Fang, Y. Chen, and N. Corporation. ICCAD, page 80. ACM, (2018)Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization.W. Fang, S. Liu, H. Zhang, and Z. Xie. CoRR, (2024)CAMU-Net: Copy-move forgery detection utilizing coordinate attention and multi-scale feature fusion-based up-sampling.K. Zhao, X. Yuan, T. Liu, Y. Xiang, Z. Xie, G. Huang, and L. Feng. Expert Syst. Appl., 238 (Part C): 121918 (March 2024)Preplacement Net Length and Timing Estimation by Customized Graph Neural Network.Z. Xie, R. Liang, X. Xu, J. Hu, C. Chang, J. Pan, and Y. Chen. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 4667-4680 (2022)FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.L. Du, T. Liang, S. Sinha, Z. Xie, and W. Zhang. FPGA, page 15-25. ACM, (2023)Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation.Z. Xie, R. Liang, X. Xu, J. Hu, Y. Duan, and Y. Chen. ASP-DAC, page 671-677. ACM, (2021)AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs.W. Fang, M. Li, M. Li, Z. Yan, S. Liu, H. Zhang, and Z. Xie. CoRR, (2024)

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Disambiguation of "Xie, Zhiyao"

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APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors.

Please choose a person to relate this publication to

Qian Xie

Zhenwei Xie

Lan Xie

Jian Xie

Yangpei Xie

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xie, Zhiyao"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors.

Please choose a person to relate this publication to

Qian Xie

Zhenwei Xie

Lan Xie

Jian Xie

Yangpei Xie

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors.