Author of the publication

Progressive random access scan: a simultaneous solution to test power, test data volume and test time.

, and . ITC, page 10. IEEE Computer Society, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling., and . J. Electron. Test., 30 (5): 569-580 (2014)Analysis and test procedures for NOR flash memory defects., and . Microelectron. Reliab., 48 (5): 698-709 (2008)An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2009)Testing Computer Hardware through Data Compression in Space and Time., and . ITC, page 83-88. IEEE Computer Society, (1983)Hypergraph Coloring and Reconfigured RAM Testing., and . IEEE Trans. Computers, 43 (6): 725-736 (1994)A Data Compression Technique for Built-In Self-Test., , and . IEEE Trans. Computers, 37 (9): 1151-1156 (1988)Correction: IEEE Transactions on Computers 38(2): 320 (1989).Modeling Detection Latency with Collaborative Mobile Sensing Architecture., , and . IEEE Trans. Computers, 58 (5): 692-705 (2009)Instruction-based delay fault self-testing of pipelined processor cores., , , and . ISCAS (6), page 5686-5689. IEEE, (2005)Theory, Analysis and Implementation of an On-Line BIST Technique., and . VLSI Design, 1 (1): 9-22 (1993)Easily Testable Two-Dimensional Cellular Logic Arrays., and . IEEE Trans. Computers, 23 (11): 1204-1207 (1974)