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Test Generation of Path Delay Faults Induced by Defects in Power TSV.

, , , , , and . Asian Test Symposium, page 43-48. IEEE Computer Society, (2013)

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Test Resource Partitioning for System-on-a-Chip., , and . Frontiers in electronic testing Kluwer / Springer, (2002)Test and Diagnosis for Small-Delay Defects., , and . Springer, (2011)The hype, myths, and realities of testing 2.5D/3D integrated circuits.. LATS, page 1. IEEE, (2016)Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3D Small-world Network-on-Chip., , , and . CoRR, (2016)Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips., and . DAC, page 173-178. ACM, (2008)Integrated Droplet Routing in the Synthesis of Microfluidic Biochips., and . DAC, page 948-953. IEEE, (2007)Multi-frequency wrapper design and optimization for embedded cores under average power constraints., , and . DAC, page 123-128. ACM, (2005)Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits., and . IEEE Des. Test, 34 (5): 72-79 (2017)Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 874-887 (2019)Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (12): 2255-2270 (2019)