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Disambiguation of "Dey, Siladitya"

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A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.

, , , , , , , , , , and . A-SSCC, page 1-3. IEEE, (2021)

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Joseph Dey

Pradip Dey

Horst Dey

Günther Dey

Rosmarie Dey

 

Other publications of authors with the same name

A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique., , , , , , , , and . IEEE J. Solid State Circuits, 55 (3): 706-718 (2020)A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM., , , , and . CICC, page 1-4. IEEE, (2014)A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (8): 2353-2364 (2018)A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation., , , and . IEEE J. Solid State Circuits, 53 (3): 799-813 (2018)350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS., , , , and . IEEE J. Solid State Circuits, 50 (8): 1833-1847 (2015)Hidden Subgroup Quantum Algorithms for a Class of Semi-Direct Product Groups., and . TQC, volume 27 of LIPIcs, page 110-117. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2014)A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS., , , , , and . VLSIC, page 256-. IEEE, (2015)A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (7): 2440-2453 (2019)A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer., , and . CICC, page 1-4. IEEE, (2019)A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation., , , and . CICC, page 1-4. IEEE, (2017)