Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.

Y. Wang, S. Dey, T. He, L. Shi, J. Zheng, M. Kareppagoudr, Y. Zhang, K. Sobue, K. Hamashita, K. Tomioka, and G. Temes. A-SSCC, page 1-3. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Manjunath Sadashiva

Bangalore Manjunath

Other publications of authors with the same name

Slewing Mitigation Technique for Switched Capacitor Circuits.M. Kareppagoudr, J. Shakya, E. Caceres, Y. Kuo, and G. Temes. IEEE Trans. Circuits Syst., 67-I (10): 3251-3261 (2020)Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits.T. He, M. Kareppagoudr, Y. Zhang, E. Caceres, U. Moon, and G. Temes. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (4): 1331-1341 (2019)Pseudo-pseudo-differential circuits.T. He, M. Kareppagoudr, U. Moon, G. Temes, and Y. Zhang. MWSCAS, page 1517-1520. IEEE, (2017)Switched-Capacitor Integrator with Slew-Rate Enhancement and Low Distortion.M. Kareppagoudr, E. Caceres, and G. Temes. MWSCAS, page 150-153. IEEE, (2021)A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3.P. Payandehnia, H. Maghami, H. Mirzaie, M. Kareppagoudr, S. Dey, M. Tohidian, and G. Temes. IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (8): 2353-2364 (2018)Pseudo-Pseudo-Differential Multibit Delta-Sigma Modulator.E. Caceres, M. Kareppagoudr, J. Shakya, and G. Temes. MWSCAS, page 675-678. IEEE, (2020)Passive slew rate enhancement technique for Switched-Capacitor Circuits.M. Kareppagoudr, E. Caceres, Y. Kuo, J. Shakya, Y. Wang, and G. Temes. MWSCAS, page 913-916. IEEE, (2019)A 13b-ENOB Noise Shaping SAR ADC with a Two-Capacitor DAC.L. Shi, Y. Zhang, Y. Wang, M. Kareppagoudr, M. Sadollahi, and G. Temes. MWSCAS, page 153-156. IEEE, (2018)A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.Y. Wang, S. Dey, T. He, L. Shi, J. Zheng, M. Kareppagoudr, Y. Zhang, K. Sobue, K. Hamashita, K. Tomioka and 1 other author(s). A-SSCC, page 1-3. IEEE, (2021)

BibSonomy

Disambiguation of "Kareppagoudr, Manjunath"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.

Please choose a person to relate this publication to

Manjunath Sadashiva

Bangalore Manjunath

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kareppagoudr, Manjunath"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.

Please choose a person to relate this publication to

Manjunath Sadashiva

Bangalore Manjunath

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.